 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| DATASHEET Imaging Imaging Product Line RA1133J Full Frame CCD Image Sensor 24 m square pitch, 1100 x 330 pixel configuration Description The RA1133J is a full frame CCD sensor with reset capabilities designed specifically for use in spectroscopy, biomedical imaging and related scientific imaging applications. The package for the array is designed with an integrated two stage thermoelectric cooler. This enables the device to be run 40 C below ambient temperature, -15 C when compared to room temperature. Its combination of very low noise and low dark current make it ideal for low light, high dynamic range and high resolution applications. MPP Operation A major source of dark current in devices such as this originates in surface states at the Si-SiO2 interface. A unigue design and process enables the RA1133J to be run in "multi-pinned phase" or MPP mode of operation. This helps eliminate dark current generation in the interface surface states. By holding the vertical clocks at negative potential during integration and horizontal signal readout, the surface will not be depleted and the surface state will not generate dark current. Features * 363,000 picture elements (pixels) in a 1100 x 330 configuration * 24 m square pixels * 2-phase buried channel process * On-chip amplifier for low noise and high speed readout * Dynamic range greater than 25,000:1 * On-chip temperature sensor * Two stage TE cooler integrated into the package * Hermetically sealed * 100% fill factor * 10 MHz data rate The imager is structured with a single output register at one end of the imaging columns. A lateral reset drain is located adjacent to this readout register which enables the dumping of accumulated charge from the array. Two phase clocks are needed to drive the readout register. Three phase clocks are needed to drive imaging cells. The array is available in a 30-pin metal package with an integrated TE cooler as shown in Figure 1. Package dimensions are shown in Figure 8. Caution: While the RA1133J imagers have been designed to resist electrostatic discharge (ESD), they can be damaged from such discharges. Always observe proper ESD precautions when handling and storing these sensors. www.perkinelmer.com/opto DSP-303.01C- 8/2002W Page 1 Full Frame CCD Sensor Imaging Area The imaging area is an array of 1100 columns (vertical CCD shift registers). Each column has 330 picture elements. The pixel size is 24 m by 24 m. The total imaging area is 26.4 mm by 7.92 mm. Typical spectral response as a function of wavelength is shown in Figure 2. This is for both the standard array and an array coated with lumogen, an UV phosphor that extends the range of the detector into the ultraviolet. In the vertical direction, each pixel corresponds to one stage (three electrodes) of the shift register. The three electrode groups are driven by three-phases (O1V O3V) brought in from both edges of the array to improve clock electrode response time. Charge packets (imaging data) in the vertical register can be shifted to the horizontal readout by clocking the three phases (O1V, O2V and O3V). A transfer gate (OTG) is provided at the interface of the vertical register. The transfer gate controls the transferring of charge into the horizontal readout register. Charge flow is from O3 gate of the vertical shift register into O1 gate of the horizontal readout register. The control function is performed by pulsing the transfer gate high to permit the charge flow from the vertical register into the horizontal register for readout. When the potential of the vertical register electrodes is held steady, a potential well is created beneath the storage gates O1V and O2V. When an image impinges on the sensing area, an electrical signal of the scene will be collected in the potential well during this integration period. Following the integration interval, the collected charge (signal) in the array can be read out as a full frame image by transferring the charge, one or more rows at a time, into the horizontal shift register. From here, the charge can be shifted serially to the output amplifier. A mechanical shutter is needed to shield the array from incident light during the readout process. A strobe illumination could be used to stimulate the shuttered mode of operation. Image smearing degrades the performance, particularly at low data rates, unless shuttering is provided. Figure 1. Pinout Configuration + O1V O3V OTG2 VLD OLG2 LS TEMP+ TEMPVSUB OTG2 O3V O1V O2V OTG1 OSG O2V OTG1 N/C VSUB LS O1H O2H OLG1 VDD VOUT VLD VSS VRD ORG VOG Figure 2. Quantum Efficiency Quantum Efficiency (%) 60 50 40 30 20 10 0 200 300 400 500 600 700 800 900 1000 1100 Wavelength, nm Figure 3. Functional Diagram O1V O2V O3V OTG Imaging Area 1100 (H) x 330 (V) - active pixels Horizontal Register The horizontal shift register is driven by two phase clocks (O1H and O2H). The horizontal register has 1100 stages plus an extension of 35 stages ( 3 dummy stages, 16 leading isolation stages and 16 trailing isolation stages). As a result, amplifier power is dissipated more efficiently and dark current generation by localized heating is minimized. O1H O2H OLG VLD Horizontal CCD Shift Output Buffer www.perkinelmer.com/opto DSP-303.01C - 8/2002W Page 2 Full Frame CCD Sensor Summing Mode At the end of the horizontal register, there is an ouput summing well which can be clocked to allow multiple-pixel summation of the scene. This summing well is located after the 19 extra stages of the horizontal register and prior to the DC biased gate (VOG) as shown in Figure 5. The summing gate (OSG) can be clocked with one of the horizontal clock phases or with its own clock generator (see Figure 4a for summing gate timing). For example, two parallel lines of charge are additively transferred into the serial register, then the summing gate is pulsed low after the charge from two serial pixels has been transferred into the summing well. Thus, the resulting signal represents the sum of charges in four (2x2) contiguous pixels from the imaging region. It effectively reduces the 1100 x 330 device to a 550 x 165 array and increases the pixel size by four times. Other variations of this technique can be useful for low-light level situations, i.e., scenes with low contrast or a low signal-tonoise ratio. There is, of course, a loss in resolution that accompanies the gain in effective pixel size. Figure 4C. Horizontal CCD Shift Register Timing Normal Mode t1 t2 t3 t4 t5 t6 t7 t8 H1 1V 2V 3V TG MPP Mode t9 t10 t11 t12 t13 t14 t15 H1 1V 2V Table 3V TG Table 2. Vertical Timing Diagram Characteristics Item Sym Min Typ Max Units Output Amplifier There is an on-chip amplifier that is located at the end of the extended shift register. The amplifier is a two stage buried channel transistor amplifier as shown in Figure 5. It is designed to operate with data rates in excess of 10 MHz. It has a bandwidth of approximately 60 MHz with a 10 pF load. Temperature Monitoring The RA1133J device has a temperature sensor integrated into the package for monitoring array temperature. FE H1 to FE 1V FE 1V to RE 3V RE 3V to FE 2V FE 2V to RE 1V RE 1V to FE 3V FE 3V to RE 2V RE 2V to FE TG FE TG to RE H1 FE H1 to RE 2V RE 2V to RE 3V RE 3V to FE 2V FE 2V to RE 1V RE 1V to FE 3V FE 3V to FE TG FE TG to RE H1 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t14 2.6 2.6 2.6 5.2 1.4 1.4 4.6 2.6 2.6 5.2 2.6 2.6 2.8 4.6 2.6 s s s s s s s s s s s s s s s Figure 4a. Horizontal CCD Shift Register Timing t1 t2 Timing Requirements The timing recommended to run the RA1133J imager in the low speed and low noise mode of operation is shown in Figures 4A, 4B, and 4C. A 50% duty cycyle, two phase clock will drive the horizontal register to its highest speed. Figure 4a shows the timing of the horizontal two phase clocks, summing well clock and reset clock. To achieve high charge transfer, serial clocks must cross between 10% and 90% of the peak voltage. In addition, the rise and fall times of the two phase clocks need to be more than 50 ns in order to prevent the injection of spurious charge into the CCD channel. O1H O2H t3 t4 t9 OSG t5 t6 t7 ORS t8 Video Output www.perkinelmer.com/opto DSP-303.01C - 8/2002W Page 3 Full Frame CCD Sensor Timing Requirements (cont.) The timing shown in Figure 4a is repeated 1100 + 35 (or more) times to allow the readout of one complete line of the image. Figure 4b shows the timing requirements for the vertical register. Overlapping of the vertical clocks are normally longer than 5 s. Rise and fall times of all clocks need to be 3 s or longer in order to prevent spurious charge into the CCD channel. All vertical clock transitions should occur when the horizontal clocks are held steady. Timing for MPP and normal mode is shown. The difference between the two modes is that during integration, all clocks must be held low for MPP mode. potential which is more positive than the low state channel potential of the transfer gate. Similar to a lateral antiblooming drain, charge will spill preferentially into the rapid discharge drain. Due to the fixed potential barrier, the HCCD cannot be completely cleared of charge and thus one horizontal shift sequence is required before resumption of valid data read. Table 1. Timing Diagram Characteristics Item Sym T1 T2 T3 T4 T5 T6 T7 T8 T9 10 100 +0 +0 50 +0 Min Typ 50 100 Max Units ns ns ns o 1, 2H rise/fall time o 1, 2H clock period o SG delay from o H2 edge o SG rise/fall time o RG delay from o SG edge o SG delay from o RG edge o RG rise/fall time o RG pulse duration o SG pulse duration 50 ns ns ns ns ns ns Array Cooling Both the dark current and the noise performance of the array can be improved by cooling. The dark current will be reduced by 50% for approximately every 6 - 8 C reduction in array temperature. Cooling can be achieved via the integrated thermoelectric cooler. The bias supplies TEC+ and TEC- electronically control this cooler. This is a two-stage cooler capable of reducing the temperature of the array 40 C from the ambient temperature. Additional cooling can be achieved by decreasing the ambient temperature or by cooling the heat sink on the TE cooler as shown in Figure 6 and Figure 7. Figure 4b. Vertical CCD Shift Register Timing and Its Relationship to Horizontal Clocks in Normal and MPP Mode Quiescent State of All Horizontal Phases During o C Transitions Horizontal Clear Out 1 1135 (+) o Clock Cycles 1135 (+) o Clock Cycles to read 1 line Region of Interest Rapid access to regions of interest is facilitated by use of a lateral charge drain. The drain is constructed adjacent to the horizontal CCD (HCCD) shift register. Unwanted lines of data are quickly disposed without the requirement for horizontal transfer. In this manner, entire lines of image data can be disposed of by a single vertical shift sequence, with a time penalty of 20 s. This is to be contrasted with the normal read sequence which includes both the vertical shift (20 s), plus readout of the 1130 horizontal elements (2260 s). As the unwanted lines are transferred from storage region into the HCCD, the horizontal phases are held high to maintain a surface o1H o2H o1V o2V o3V oTG End Integration Period Repeat 330(+) Times to Read Out the Entire Image Start Integration Period Normal Mode o1V o2V o3V oTG MPP Mode www.perkinelmer.com/opto DSP-303.01C - 8/2002 Page 4 Full Frame CCD Sensor Figure 5. Output Structure VRD ORG VOG OSG VDD O1H Two Stage Amplifier VSUB VOUT VSS VSS Figure 6. TEC Current vs. Chip Temperature (Ambient Temperature) Current to Thermo-Electric Cooler, Amp .5 1.0 1.5 2.0 0 0 -10 -20 TChip - T Ambient, C 2.5 2.3 C/W Heat Sink -30 -40 -50 -60 -70 -80 1.8C/W Heat Sink 1.3 C/W Heat Sink .5 C/W Heat Sink 0 C/W Heat Sink Figure 7. Heat Sink Temperature vs. Chip Temperature Heat Sink Temperature THot, C 10 0 I = .5A TEC Current -10 I = 1.1A TEC Current -20 I = 2.0A TEC Current -30 I = 2.5A TEC Current -40 20 30 40 50 60 Chip Temperature TCPLP, C -50 www.perkinelmer.com/opto DSP-303.01C - 8/2002 Page 5 Full Frame CCD Sensor Figure 8. Package Dimensions 0.110 (2.794) 15 1.150 (29.21) 0.523 (13.28) Image Center Die Apeture 1 4 x O0.125 holes 1.100 0.880 (27.94) (22.35) 0.440 (11.18) Measurements in inches (millimeters) Pixel 1 16 30 0.158 (4.013) 2.320 (58.93) 2.530 (64.26) 0.105 (2.667) + 0.115 /- 0.010 + (2.921 /- 0.254) Image surface to inside of window 30 x O0.025 pin 0.330 (8.382) 0.620 (15.74) 0.451 +/- 0.010 (11.45 +/- 0.254) Bottom surface to image surface 0.565 (14.35) 0.100 (Both sides) (2.540) 1.400 (35.56) TEC + TEC - 0.420 (10.67) 0.600 (15.24) 1.300 /- 0.015 + (33.02 /- 0.381) + 2 x O0.08 pin Table 3. Absolute Maximum Ratings Min Storage Temperature Operating Temperature - 55C - 55C Max + 85C + 85C Table Table 4. Typical Device Specifications Parameter Format Pixel Size Imaging Area 1 Dynamic Range 2 Full Well Charge Saturation Voltage 3 Dark Current MPP Photo Response Non Uniformity Dark Signal Uniformity Charge Transfer Efficiency Output Amplifier Gain Operating Frequency Read Noise 4 Sym Min Typ 1100 x 330 24 x 24 26.4 x 7.92 25,000:1 300 1200 1 5 2 0.99995 4 10 Max Units m mm KemV pA/cm2 % % V/eMHz e- DR Q SAT V SAT DL PRNU DSNU CTE fclock 250 1000 3 10 5 0.9999 15 Notes: 1. Full well/read noise, MPP mode 2. RLoad = 5.1 kOhms, MPP mode 3. MPP mode at -15 C 4. Measured at 500 kHz at -15 C www.perkinelmer.com/opto DSP-303.01C - 8/2002W Page 6 Full Frame CCD Sensor Table 3. Table 5. Recommended Operating Conditions Pin # 24, 25 3, 29 15 1, 12 2, 11, 13, 30 5, 23 17 16 22 4, 20 18 6, 26 19 9, 27 Signal O1H, O2H OTG OSG O1V (MPP) O2V, O3V OLG ORG VOG VDD VLD VRD LS VSS VSUB Function Horizontal Clocks Transfer Gate Clock Summing Gate Clock Vertical Clock (MPP Phase) Vertical Clocks Lateral Charge Gate Reset Gate Output Gate Amplifier Voltage Supply Lateral Charge Drain Amplifier Reset Drain Light Shield Video Amplifier Source Substrate Bias High Low High Low High Low High Low High Low High Low High Low Typ 5 0 4 -8 5 0 4 -9 2 -11 5 0 8 0 3 14 13 10 GND GND -2 Tolerance 5% 10% 5% 5% 5% 5% 10% 5% 5% 5% 5% 5% 5% 5% Table 6. Pinout Descriptions Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Sym O1V O3V OTG2 VLD OLG2 LS TEMP+ TEMPVSUB OTG2 O 3V O 1V O 2V OTG1 O SG Function Vertical Phase 1 Vertical Phase 3 Transfer Gate 2 Lateral Charge Drain Lateral Charge Gate 2 Light Shield Temp+ TempSubstrate Transfer Gate 2 Vertical Phase 3 Vertical Phase 1 Vertical Phase 2 Transfer Gate 1 Summing Gate Pin # 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Sym VOG O RG VRD VSS VLD VOUT VDD O LG1 O 2H O 1H LS V SUB N/C O TG1 O 2V Function Output Gate Reset Gate Reset Drain Video Amplifier Source Lateral Charge Drain Video Output Video Amplifier Drain Lateral Charge Gate 1 Horizontal Phase 2 Horizontal Phase 1 Light Shield Substrate No Connection Transfer Gate 1 Vertical Phase 2 www.perkinelmer.com/opto DSP-303.01C - 8/2002W Page 7 Full Frame CCD Sensor Ordering Information While the information provided in this data sheet is intended to describe the form, fit and function for this product, PerkinElmer reserves the right to make changes without notice. Table 7. Ordering Information Part Number RA1133JAS-912 For more information e-mail us at For more information e-mail us at opto@perkinelmer.com or visit our web site at www.perkinelmer.com/opto. All values are nominal; specifications subject to change without notice. Table 8. Sales Offices North America United States PerkinElmer Optoelectronics 2175 Mission College Blvd. Santa Clara, CA 95054 Toll Free: 800-775-OPTO (6786) Phone: +1-408-565-0830 Fax: +1-408-565-0703 Europe Germany PerkinElmer Optoelectronics GmbH Wenzel-Jaksch-Str. 31 D-65199 Wiesbaden, Germany Phone: +49-611-492-570 Fax: +49-611-492-165 Asia Japan PerkinElmer Optoelectronics NEopt. 18F, Parale Mitsui Building 8 Higashida-Cho, Kawasaki-Ku Kawasaki-Shi, Kanagawa-Ken 210-0005 Japan Phone: +81-44-200-9170 Fax: +81-44-200-9160 www.neopt.co.jp 47 Ayer Rajah Crescent #06-12 Singapore 139947 Phone: +65-770-4925 Fax: +65-777-1008 Singapore (c) 2001 PerkinElmer Inc. All rights reserved. PerkinElmer, the PerkinElmer logo and the stylized "P" are trademarks of PerkinElmer, Inc. Reticon is a registered trademark of PerkinElmer, Inc. DSP-303.01C - 8/2002W www.perkinelmer.com/opto Page 8 |
Price & Availability of RA1133JAS
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |